Semiconductor memory devices are essential to any modern digital electronic system. Semiconductor memory may be categorized into random access memory (RAM) and read only memory (ROM). In contrast to RAM, ROM memory is non-volatile and as the name suggests, ROMs allow retrieval of previously stored information. Depending on the method used to write information into a ROM, ROM memory is further categorized as masked ROM and programmable ROM. Masked ROM refers to arrays of memory where data is written onto the ROM at the chip fabrication time. In contrast, programmable ROMs allow data to be written onto the chip after fabrication. Data in a programmable ROM may be erased using ultraviolet light, referred to as an erasable read only memory (EPROM). Alternatively, data may be erased from the EPROM using high electrical voltage. EPROMs requiring high voltage to erase stored data are referred to as electrically erasable programmable read only memory (EEPROM).
Flash memory is similar to an EEPROM. FIG. 1 is a cross section view of an exemplary prior art flash memory device in the erase mode. As shown in FIG. 1, a common flash memory device 10 is based on an n-channel MOSFET, including a source 12, a drain 14, a control gate 16, and a floating gate 18. The flash memory device 10 is shown in the erase mode, with P substrate 20 connected to VPP usually at larger than 9 volts. The bit line coupled to the drain 14 and source line 12 are kept open (or floating). The control gate 16 is connected to negative voltage VCG.
The threshold voltage of a flash memory device is programmed by either storing at, or ejecting from, electrons at the floating gate of a MOS transistor through channel hot-electron injection or Fowler-Nordheim tunneling mechanisms.
The application of a high voltage (e.g. 12 volts) to the control gate 16 while the source 12 is grounded and the drain (bit line) 14 is sufficiently high voltage such as 5 volts, causes the accumulation of electrons at the floating gate 18, resulting in a higher threshold voltage. The higher threshold voltage results in the MOSFET device that remains turned off, during the application of a low voltage read signal (e.g. 5 volts in the control gate 16). This in turns results in a reading of high voltage (usually 5 volts), at the bit line, corresponding to a logic level 0 or programmed state.
Alternatively, in the erase mode of operation, the application of high voltage (e.g. 9 volts) to the P-substrate 20 with negative voltage to the control gate 16, with the source 12 and the drain 14 kept open, creates high electric field between the control gate 16 and the P-substrate 20, causing the electrons stored at the floating gate 18 to eject through a Fowler-Nordheim tunneling effect to the P-substrate 20. This reduction of the number of stored electrons at the floating gate 18 reduces the threshold voltage of the MOSFET device 10. The lowered threshold voltage allows the MOSFET device 10 to be turned on, with the application at the control gate 16 of a 5 volts read signal. Thus, during a read operation, the bit line (drain 14) is brought down to ground, resulting in a reading of a logical 1 or erased state.
In a traditional bi-level flash memory circuit, the gap between the zero logic level corresponding to the lower threshold voltage and the one logic level, corresponding to the higher threshold voltage is typically in the order of two to three volts. Therefore, relatively minor disturbances in the order of couple of hundred milli-volts (mV) will not affect the operation of a bi-level flash memory cell. One cause of such shifts in the threshold voltage levels may be the de-trapping of holes (positive charges) at the tunneling oxide or tunneling oxide-silicon interface underneath of the floating gate, resulting in a shift of the threshold voltages toward higher voltage levels. Similarly, the de-trapping of electrons (negative charges) at the tunneling oxide or tunneling oxide-silicon interface may result in a lower threshold voltage than desired. In a bi-level flash memory cell, even the lower threshold voltage shifts several hundreds of milli-volts, the voltage gap between the high and low threshold voltage levels is wide enough to allow for a satisfactory operation of the device.
Reducing memory density is a constant goal of designers. In the past, reducing the cell size has been the primary technique of reducing memory density. Another method of improving the effective density of a memory arrays is operating the flash memory devices in multi-level mode of operation, allowing for a single memory cell to store a couple of bits of data.
FIG. 2 illustrates a multilevel cell threshold voltage distribution, allowing a single cell to store 2 bits per cell. The inherent feature of flash memory, namely the ability to change or program the threshold voltage allows a flash memory cell to operate at multiple levels corresponding to storage of multiple bits in a single memory cell. The number of states per cell is limited by several factors including the available charge range, the accuracy of the programming, erase and read operations, and the disturbances of a state over time. One such disturbance of a state may be caused by de-trapping of the holes, which are trapped at the tunneling oxide or tunneling oxide-silicon interface, resulting in a shift in the threshold voltage corresponding to a level of a multi-level cell. Experimental results have shown that the de-trapping of the trapped holes at the tunneling oxide or tunneling oxide-silicon interface begins to affect the operation of the multi-level cell within less than ten minutes after the flash cell has received some standard write-erase cycling (such as 10,000 cycles), simulating the device in real operating conditions.
FIG. 3 illustrates an experimentally determined graph of the threshold level distributions for a flash memory cell. Because of the de-trapping of the trapped holes at the tunneling oxide or tunneling oxide-silicon interface, the threshold voltages corresponding to each of the four logic levels shown in FIG. 3 tends to shift to the right, i.e. toward the next higher logic level. The drift additionally reduces the gap between the various levels, thus reducing the program and read accuracy of the cell and resulting in a deterioration of the read disturb for each of the different multi-level cell (MLC) levels. Even a shift of a couple of hundred milli-volts may be significant enough to result in problematic operation of the multi-level memory cell.
It is therefore desirable to provide a method of programming and erasing of data into a multi-level cell that would result in a lesser disturbance of the read/write accuracy of a multi-level flash memory cell.
It is further desirable that such a method be easily applicable to multi-level cell operation.